//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_UART_H__
#define __ELASTOS_UART_H__

#define COMPORT_AVAILABLE(comPort) \
        (ComPort1 == (comPort))

// UART IO base address
#define _UART1_IOBASE       ((ioport_t)0x80000000)
#define _UART2_IOBASE       ((ioport_t)0x80001000)

#define COMPORT_IOBASE(comPort) \
        ((ComPort1 == (comPort))? _UART1_IOBASE : _UART2_IOBASE)

// UART Irq
#define _UART1_TXIRQ        12
#define _UART1_RXIRQ        13
#define _UART2_TXIRQ        28
#define _UART2_RXIRQ        29

// UART registers' address
#define _SYSCON(base)       ((ioport_t)((base) + 0x100))
#define _SYSFLG(base)       ((ioport_t)((base) + 0x140))
#define _INTSR(base)        ((ioport_t)((base) + 0x240))
#define _INTMR(base)        ((ioport_t)((base) + 0x280))
#define _UARTDR(base)       ((ioport_t)((base) + 0x480))
#define _UBRLCR(base)       ((ioport_t)((base) + 0x4c0))

// SYSCON1-2 The System Control Register 1-2
#define _UARTEN         __32BIT(8)

// System Status Flags Register
#define _UBUSY          __32BIT(11)
#define _URXFE          __32BIT(22)
#define _UTXFF          __32BIT(23)

// UARTDR1-2, UART1-2 Data Registers
#define _FRAME          0x0100
#define _PARITY         0x0200
#define _OVERRUN        0x0400
#define _ERRMASK        0x0700

// UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers
#define _BRD_115200_16  0x00000001
#define _BRD_76800_16   0x00000002
#define _BRD_57600_16   0x00000003
#define _BRD_38400_16   0x00000005
#define _BRD_19200_16   0x0000000b
#define _BRD_14400_16   0x0000000f
#define _BRD_9600_16    0x00000017
#define _BRD_2400_16    0x0000005f
#define _BRD_1200_16    0x000000bf
#define _BRD_110_16     0x0000082e

#define _BREAK          0x00001000
#define _PRTEN          0x00002000
#define _EVENPRT        0x00004000
#define _XSTOP          0x00008000
#define _UFIFOEN        0x00010000
#define _WRDLEN_5       0x00000000
#define _WRDLEN_6       0x00020000
#define _WRDLEN_7       0x00040000
#define _WRDLEN_8       0x00060000

// INTSR1-2 Interrupt Status Register 1
#define _TXINT          0x1000
#define _RXINT          0x2000
#define _MSINT          0x4000

// INTMR1-2 Interrupt Mask Register
#define _TXINTM         0x1000
#define _RXINTM         0x2000
#define _MSINTM         0x4000

#endif // __ELASTOS_UART_H__
